Embodiments of the inventive concepts relate to semiconductor devices having active regions of different conductivity types.
Various methods of forming upper ends of gate electrodes at certain levels while simplifying a process in a semiconductor device having an NMOS region and a PMOS region have been studied. A P-type channel region formed in the NMOS region and an N-type channel region formed in the PMOS region may have different heights. The P-type channel region and the N-type channel region having the different heights may be an obstacle to formation of gate electrodes.
For example, an N-type fin may be formed on an N-well, and a P-type fin may be formed on a P-well. A channel SiGe layer may be formed on the N-type fin using a Selective Epitaxial Growth (SEG) technique. A first preliminary gate may be formed on the channel SiGe layer, and a second preliminary gate may be formed on the P-type fin. A first source/drain may be formed on both sides of the first preliminary gate. A second source/drain may be formed on both sides of the second preliminary gate. An interlayer insulating layer may be formed on the first source/drain and the second source/drain. A first trench and a second trench may be formed by removing the first preliminary gate and the second preliminary gate. A first gate and a second gate may be formed in the first trench and the second trench. The first gate and the second gate may be referred to as a replacement gate.
A process of forming the first gate and the second gate may include a Chemical Mechanical Polishing (CMP) process. The channel SiGe layer may protrude at a level higher than the P-type fin. Various problems may arise from a height difference between the first gate and the second gate in the CMP process.